Experience

Education

• Ph.D. in Computer Engineering, Duke University, 2022
  • Advisor: Prof Yiran Chen, Prof Hai Li.
  • Grade: 3.94/4.0.
• B.Eng. in ECE, City University of Hong Kong, 2017
  • First Class Honours. Full Tuition Scholarship.
  • Major Grade: 4.16/4.3.

Service

• Technical Program Committee Member of ASP-DAC 2023, 2025
• Technical Program Committee Member of DATE, 2025
• Technical Program Committee Member of IEEE/ACM ICCAD 2023, 2024
• Technical Program Committee Member of IEEE MLCAD 2024
• Technical Program Committee Member of IEEE LAD 2024
• Financial Chair, IEEE CEDA Hong Kong, 2024
• Seminar Chair, IEEE CEDA Hong Kong, 2023
• Publicity Chair, IEEE CEDA Hong Kong, 2022
• Reviewer of ACM TODAES (Distinguished Reviewer), ACM JETC, ACM TECS, Springer JCST, IEEE TCAD, IEEE TCAS-I, IEEE ESL, IEEE Design & Test, IEEE CAL, IEEE SPL, NeurIPS

Teaching Experience

• Instructor of ELEC 6910D, HKUST, 24 Spring
  • ELEC 6910D: Electronic Design Automation for VLSI Design (Graduate)
  • Course Developer, the 1st course on EDA algorithm in HKUST
  • Covers VLSI design flow, synthesis, floorplan, placement, routing, etc.
• Instructor of ELEC 2350, HKUST, 23 Spring, 23 Fall, 24 Fall
  • ELEC 2350: Introduction to Computer Organization and Design (Undergraduate)
  • One of the four core (required) courses in ECE, enrollment > 100 students
  • Covers basic number system, MIPS ISA, pipelined CPU architecture, cache, etc.
  • Evaluation 23’Fall (4.40 / 5.0, School UG Course Mean = 4.03)
  • Evaluation 23’Spring (4.24 / 5.0, School UG Course Mean = 4.00)
• TA of ECE 586 and ECE350, Duke University, 2021
  • ECE 586: Vector Space Methods with Applications. (Graduate)
  • ECE 350: Digital Systems. (Undergraduate)
• EDA Supporter of ECE 532 and ECE 539, Duke University, 2021
  • ECE 532: Analog Integrated Circuit Design. (Graduate)
  • ECE 539: CMOS VLSI Design Methodologies. (Graduate)

Work Experience

• Assistant Professor, HKUST, 2022-now
  • Electronic and Computer Engineering (ECE) Department.
  • PhD supervisor, Principal Investigator
• Part-time EDA Administrator, Duke University, 2020-2022
  • Purchasing and providing help on all EDA tools for teaching and research purposes at Duke University.
• Research Intern, Arm, June 2020 – Nov 2020
  • Developed the first runtime on-chip power monitor that simultaneously achieves per-cycle resolution and less than 1% area overhead without compromising accuracy.
  • The overall framework automatically generates training data, develops the model, and constructs the power monitor with minimum designer interference. Verified on multiple industry-standard CPU cores including ARM Neoverse N1 and Cortex-A77.
• Software Engineer Intern, Synopsys, May 2019 – Aug 2019
  • Developed a light-weighted linear model to estimate transition violation on the clock tree.
  • Model is integrated into IC Compiler II and proves to improve clock tree quality by guiding CTS with early feedback.
• Research Intern, Nvidia, Sep 2018 – Dec 2018
  • Developed a customized CNN model for IR drop prediction. By incorporating switching time into power map features, this is the first design-independent estimator for both vector-based and vectorless IR drop.
  • After integrating it into their in-house IR mitigation flow, hotspots in latest designs are reduced by 30%.
• Software Engineer Intern, Cadence, June 2018 – Aug 2018
  • Developed deep neural network models for very early routability prediction even before the placement optimization. This is an early effort on routability estimation in the EDA industry.