Education

• Ph.D. in Computer Engineering, Duke University, 2022
  • Advisor: Prof Yiran Chen, Prof Hai Li.
  • Grade: 3.94/4.0.
• B.Eng. in ECE, City University of Hong Kong, 2017
  • First Class Honours. Full Tuition Scholarship.
  • Major Grade: 4.16/4.3.

Award

• ACM Outstanding Dissertation Award in EDA, 2023
• EDAA Outstanding Dissertation Award, 2023
• ASP-DAC 2023 Best Paper Award, 2023
• ASP-DAC 2023 Best Paper Candidate, 2023
• ACM TODAES Distinguished Reviewer, 2022
• ACM SIGDA Best Research Poster Award, 2022
• IEEE/ACM MICRO 2021 Best Paper Award, 2021
• ECE Ph.D. Fellowship, Duke University, 2018
• Dean’s List for all 8 semesters, CityU HK, 2013-2017
• Full Tuition Scholarship for 4 years, CityU HK, 2013-2017

Service

• Technical Program Committee Member of ICCAD 2023
• Technical Program Committee Member of ASP-DAC 2023
• Seminar Chair, IEEE CEDA Hong Kong, 2023
• Publicity Chair, IEEE CEDA Hong Kong, 2022
• Reviewer of ACM TODAES (Distinguished Reviewer), ACM JETC, ACM TECS, Springer JCST
• Reviewer of IEEE TCAD, IEEE TCAS-I, IEEE ESL, IEEE Design & Test, IEEE CAL

Work Experience

• Part-time EDA Administrator, Duke University, 2020-2022
  • Purchasing and providing help on all EDA tools for teaching and research purposes at Duke University.
• Research Intern, Arm, June 2020 – Nov 2020
  • Advisor: Xiaoqing Xu, Shidhartha Das, Brian Cline
  • Developed the first runtime on-chip power monitor that simultaneously achieves per-cycle resolution and less than 1% area overhead without compromising accuracy.
  • The overall framework automatically generates training data, develops the model, and constructs the power monitor with minimum designer interference.
  • It is verified on multiple industry-standard CPU cores including ARM Neoverse N1 and Cortex-A77.
• Software Engineer Intern, Synopsys, May 2019 – Aug 2019
  • Advisor: Anand Rajaram, Min Pan, Aiqun Cao
  • Developed a light-weighted linear model to estimate transition violation on the clock tree.
  • The model is integrated into IC Compiler II and proves to improve clock tree quality by guiding CTS with early feedback.
• Research Intern, Nvidia, Sep 2018 – Dec 2018
  • Advisor: Haoxing (Mark) Ren, Brucek Khailany
  • Developed a customized CNN model for IR drop prediction. By incorporating switching time into power map features, this is the first design-independent estimator for both vector-based and vectorless IR drop.
  • After integrating it into their in-house IR mitigation flow, hotspots in latest designs are reduced by 30%.
• Software Engineer Intern, Cadence, June 2018 – Aug 2018
  • Advisor: Jie (Jack) Chen, Weibin Ding
  • Developed deep neural network models for very early routability prediction even before the placement optimization. This is an early effort on routability estimation in the EDA industry.

Teaching Experience

• Instructor of ELEC 2350, HKUST, 2023
  • ELEC 2350: Introduction to Computer Organization and Design (Undergraduate)
• TA of ECE 586, Duke University, 2021
  • ECE 586: Vector Space Methods with Applications. (Graduate)
• TA of ECE 350, Duke University, 2021
  • ECE 350: Digital Systems. (Undergraduate)
• EDA Supporter of ECE 532, Duke University, 2021
  • ECE 532: Analog Integrated Circuit Design. (Graduate)
• EDA Supporter of ECE 539, Duke University, 2021
  • ECE 539: CMOS VLSI Design Methodologies. (Graduate)